| VLLP01 |
A LOW POWER AND LOW AREA ROUTER WITH CONGESTION |
|
| VLLP02 |
MULTI-CONTEXT TCAM-BASED SELECTIVE COMPUTING- DESIGN SPACE EXPLORATION FOR A LOW-POWER NN |
|
| VLLP03 |
ULTRALOW-VOLTAGE RETENTION SRAM WITH A POWER GATING CELL ARCHITECTURE USING HEADER AND FOOTER POWER-SWITCHES |
|
| VLLP04 |
HIGH THROUGHPUT LOW COMPLEXITY AND LOW POWER EPIBM RS DECODER USING FRACTIONAL FOLD |
|
| VLLP05 |
DATA RETENTION BASED LOW LEAKAGE POWER TCAM FOR NETWORK PACKET ROUTING |
|
| VLLP06 |
AN ERROR COMPENSATION TECHNIQUE FOR LOW-VOLTAGE DNN ACCELERATORS |
|
| VLLP07 |
LOW-POWER TERNARY MULTIPLICATION USING APPROXIMATE COMPUTING |
|
| VLLP08 |
ARCHITECTURAL EXPLORATION FOR ENERGY-EFFICIENT FIXED-POINT KALMAN FILTER VLSI DESIGN |
|
| VLLP09 |
DESIGN OF ULTRA-LOW POWER CONSUMPTION APPROXIMATE 4-2 COMPRESSORS BASED ON THE COMPENSATION CHARACTERISTIC |
|
| VLLP10 |
MULTI-TARGET ADAPTIVE RECONFIGURABLE ACCELERATION FOR LOW-POWER IOT PROCESSING |
|
| VLLP11 |
FAST BINARY COUNTERS AND COMPRESSORS GENERATED BY SORTING NETWORK |
|
| VLLP12 |
LOW POWER FPGA BASED IMPLEMENTATION OF CORDIC ARCHITECTURE |
|
| VLLP13 |
WIDELY TUNABLE LOW PASS GM? C FILTER FOR BIO-MEDICAL APPLICATIONS |
|
| VLLP14 |
LOW-POWER AND FAST FULL ADDER BY EXPLORING NEW XOR AND XNOR GATES FOR HIGH-SPEED FPGA ARCHITECTURES |
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