FPGA SIGNAL PROCESSING

PROJECT CODE PROJECT TITLE
VLCS1 EFFICIENT FPGA-BASED VLSI ARCHITECTURE FOR DETECTING R-PEAKS IN ELECTROCARDIOGRAM SIGNAL BY COMBINING SHANNON ENERGY WITH HILBERT TRANSFORM
VLCS2 VLSI DESIGN OF LOW-COST AND HIGH-PRECISION FIXED-POINT RECONFIGURABLE FFT PROCESSORS
VLCS3 A UNIVERSAL STRING MATCHING APPROACH TO SCREEN CONTENT CODING
VLCS4 A NANO-WATT ECG FEATURE EXTRACTION ENGINE IN 65NM TECHNOLOGY
VLCS5 AN ADAPTIVE MECHANISM FOR DESIGNING EFFICIENT SNOOP FILTERS
VLCS6 AN EFFICIENT FAULT-TOLERANCE DESIGN FOR INTEGER PARALLEL MATRIX–VECTOR MULTIPLICATIONS
VLCS7 MEMORY-BASED ARCHITECTURE FOR MULTICHARACTER AHO–CORASICK STRING MATCHING
VLCS8 MODULAR DESIGN OF HIGH-EFFICIENCY HARDWARE MEDIAN FILTER ARCHITECTURE
VLCS9 DESIGN AND CHARACTERIZATION OF A LOW-COST FPGA-BASED TDC
VLCS10 ENHANCING SENSOR PATTERN NOISE VIA FILTERING DISTORTION REMOVAL FOR HD CAMERA APPLICATIONS
VLCS11 A DETERMINISTIC APPROACH TO DETECT MEDIAN FILTERING IN 1D DATA FOR MOTION ESTIMATION ALGORITHM
VLCS12 FAST SPECTRUM ANALYSIS FOR AN OFDR USING THE FFT AND SC COMBINATION APPROACH FOR ECG SIGNAL ANALYSIS
VLCS13 FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON BINARY SIGNED-DIGIT REPRESENTATION FOR LOW FIBER OPTICS COMMUNICATION
VLCS14 FAULT TOLERANT PARALLEL FFTS ARCHITECTURE USING AN HIGH SPEED PARALLEL ERROR CORRECTION CODES AND PARSEVAL CHECKS
VLCS15 A HIGHLY CUSTOMIZABLE LOW-LATENCY COMMUNICATION MAC ARCHITECTURE
VLCS16 SOURCE CODING AND PREEMPHASIS FOR DOUBLE-EDGED PULSE WIDTH MODULATION SERIAL COMMUNICATION FOR DOUBLE DYNAMIC RATE BASED WIRELESS COMMUNICATION
VLCS17 A REAL-TIME FAULT AWARE NETWORK-ON-CHIP ARCHITECTURE WITH AN EFFICIENT GALS IMPLEMENTATION
VLCS18 ASSESSING THE SUITABILITY OF KING TOPOLOGIES FOR INTERCONNECTION NETWORKS
VLCS19 A NEW CDMA ENCODING-DECODING METHOD FOR ON-CHIP COMMUNICATION NETWORK
VLCS20 ALGORITHM AND ARCHITECTURE OF CONFIGURABLE JOINT DETECTION AND DECODING FOR MIMO WIRELESS COMMUNICATIONS WITH CONVOLUTIONAL CODES