| VLCR01 |
RELIABLE CRC-BASED ERROR DETECTION CONSTRUCTIONS FOR FINITE FIELD MULTIPLIERS WITH APPLICATIONS IN CRYPTOGRAPHY |
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| VLCR02 |
HIGH-SPEED MODULAR MULTIPLIER FOR LATTICE-BASED CRYPTOSYSTEMS |
|
| VLCR03 |
AREA-EFFICIENT NANO-AES IMPLEMENTATION FOR INTERNET-OF-THINGS DEVICES |
|
| VLCR04 |
AREA-TIME EFFICIENT HARDWARE ARCHITECTURE FOR SIGNATURE BASED ON ED448 |
|
| VLCR05 |
AMNESIAC DRAM- A PROACTIVE DEFENSE MECHANISM AGAINST COLD BOOT ATTACKS |
|
| VLCR06 |
A MULTIMODE CONFIGURABLE PHYSICALLY UNCLONABLE FUNCTION WITH BIT-INSTABILITY-SCREENING AND POWER-GATING STRATEGIES |
|
| VLCR07 |
MITIGATING CROSS-CORE CACHE ATTACKS VIA SUSPICIOUS TRAFFIC DETECTION |
|
| VLCR08 |
A RESIDUAL CHAOTIC SYSTEM FOR IMAGE SECURITY AND DIGITAL VIDEO WATERMARKING |
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| VLCR09 |
DIFFERENTIAL FAULT ATTACK ON KREYVIUM & FLIP |
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| VLCR10 |
HARDWARE PRIVATE CIRCUITS- FROM TRIVIAL COMPOSITION TO FULL VERIFICATION |
|
| VLCR11 |
VISE- COMBINING INTEL SGX AND HOMOMORPHIC ENCRYPTION FOR CLOUD INDUSTRIAL CONTROL SYSTEMS |
|
| VLCR12 |
A CASTLE WITH TOWERS FOR RELIABLE, SECURE PHASE-CHANGE MEMORY |
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| VLCR13 |
HARDWARE ACCELERATION OF HASH OPERATIONS IN MODERN MICROPROCESSORS |
|
| VLCR14 |
SCHNORR-BASED IMPLICIT CERTIFICATION- IMPROVING THE SECURITY AND EFFICIENCY OF VEHICULAR COMMUNICATIONS |
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| VLCR15 |
HIGH-PARALLELISM HASH-MERGE ARCHITECTURE FOR ACCELERATING JOIN OPERATION ON FPGA |
|
| VLCR16 |
SECURE DOUBLE RATE REGISTERS AS AN RTL COUNTERMEASURE AGAINST POWER ANALYSIS ATTACKS |
|
| VLCR17 |
COIN FLIPPING PUF- A NOVEL PUF WITH IMPROVED RESISTANCE AGAINST MACHINE LEARNING ATTACKS |
|
| VLCR18 |
EMBEDDING ENCRYPTION AND MACHINE LEARNING INTRUSION PREVENTION SYSTEMS ON PROGRAMMABLE LOGIC CONTROLLERS |
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